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Author: Admin | 2025-04-28
Conference Chairman Jake Buurma Technical Program Chairman We extend our thanks to the CICC Technical Program committee and our dedicated conference staff for all of their support. It's through their diligent efforts that we keep CICC the best place to discover the latest integrated circuit design techniques, learn of the newest product announcements and debate the winningest business strategies. Custom ICs are the very center of a fast moving market with global competition, you can't afford to miss it!Architecture and Design Flow for a Highly Efficient Structured ASICIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured application specific integrated circuits (sASICs) offer a middle ground in price and performance between ASICs and field-programmable gate arrays (FPGAs) by sharing masks across different designs. In this paper, two sASIC architectures are proposed, the first being based on three-input lookup-tables, and the second on AOI22 gates. The sASICs are programmed using a standard-cell compatible design flow. They are customized using a minimum of three masks, i.e., two metals and one via. The area and delay of the sASIC are compared with ASICs and FPGAs. Results over a set of benchmark circuits show that our AOI22-based sASIC had an average of 1.76x/1.41x increase in area/delay compared to ASICs, a considerable improvement compared with the 26.56x/5.09x increase for FPGAs. This is, to the best of our knowledge, the best performance reported in the literature for a practical sASIC. A prototype using the sASIC was fabricated using a universal machine control 0.13-µm mixedmode/RF process. It was fully verified using scan and functional tests, and used in a demonstration system.An Optimized Power Performance and Area in ASIC Physical DesignInternational Journal of Electronics, Electrical and Computational System, 2017For Moore’s law to continue to be pragmatically valid, new process technologies must provide more than the projected increases in density, chip capacity, chip level performance or, performance vs. power-improvement which has been increasingly difficult to achieve. This paper deals with study and implementation of practices to get better PPA in ASIC physical design which is applicable to all digital circuits, both combinational and sequential. Various Place and Route techniques are used to achieve this using Cadence’s SOCE. The general Place and Route flow involves Floor planning, Power planning, Placement, CTS, Routing, Parasitic extraction, Timing and Power analysis. Apart from these stages, there are intermediate stages which allow for timing optimizations. A reference block is chosen and multiple experiments are performed with flow variations at each of Place and Route stage targeting PPA and frequency of 1.4GHz using 14nm technology. Generalized flow is tweaked to achieve the better PPA. All experimental data captured and concluded.
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